Optical ArF (wavelength: 193 nm) DUV immersion lithography with NA=1.35 can print half-pitch features as small as 38 nm. The next-generation EUV lithography (EUVL) technology has been delayed for several times due to its limitations in power source, throughput, resist line edge roughness (LER) and mask defect issues [1]. Therefore, a paradigm shift in patterning technology, from mainly relying on scanners' optical resolution capability to adopting spacer based frequency multiplication techniques, has occurred in the semiconductor industry to continue IC scaling.
Spacer based self-aligned multiple patterning techniques [2-4] such as double (SADP), triple (SATP), quadruple (SAQP) schemes, when combined with ArF DUV immersion lithgraphy, can potentially drive the resolution of IC features down to about 10 nm (half pitch). By designing various mandrel patterns which further define the route of the spacers formed on their sidewall, some multiple patterning techniques are more capable of driving up the feature density, while others are favorable to reducing process complexity with less masks and allowing more 2-D design flexibility. For example, the self-aligned double patterning (SADP) process has been used in NAND flash manufacturing from 35 nm to 19 nm node (half pitch); and gradually extended to logic micro-processor patterning recently [2]. Other more aggressive frequency multiplication techniques such as self-aligned triple (SATP, [3]) and quadruple (SAQP, [4]) processes have also been developed recently. It was demonstrated that by adding only one extra CVD/spacer step, the SATP process gains 50% improvement in density compared with a SADP process, and allows complex 2-D layout using less masks than SAQP process. For sub-10 nm patterning capability, the semiconductor industry has not found a cost-effective solution except turning to expensive EUVL which however will not be ready for high-volume manufacturing in time.
To overcome the scaling barriers towards sub-10 nm (half-pitch) nodes, a self-aligned frequency sextupling (or self-aligned sextupling patterning, referred to herein as “SASP” process) technique is invented. The SASP process based mask design method to release the overlay requirement for memory (e.g., NAND flash and DRAM) manufacturing is also invented. It provides a production-worthy method for the semiconductor industry to continue device scaling beyond the 10 nm in a timely manner with no need of EUVL technology.